Group: Bjøn-Hugo Nilsen, Harald Hanssen and Susanne Ingebrigtsen
Introduction
In this assignment we were to implement a simulator for a subset of the MIPS R2000 architecture. The code for the controller should be auto generated from state diagram drawings made in IAR visualSTATE. The datapath had to be written from scratch in C.
The assembly program uses the following MIPS instructions:
lw
sw
R-type (add, sub, or, and, slt)
addi
bne
j
syscall (only need to support print_int)
Implementing the clock
We used a very simple implementation of
the clock, taking advantage of the OS_Wait function and the event queue. We had
an event named clocktick, that would, when called upon by being added to the
event queue would trigger an state shift in the controller. The clock is not set
with an certain cycle time, instead it uses so much time as it takes to execute
the control signals and code.
The design and datapath
In the lecture notes we were given step-by-step guide on how to design a processor, and we used the datapath components described in Patterson/Hennesy's Computer Organization & Desgin. The datapath is a multicycle design. Note that we put an extra inverter from the ZERO output signal from the ALU.We did this because we used branch not equal instead of branch equal.
Assemble controller
We analyzed each instruction to determine setting of control points that effect register transfer and datapath operations, and implemented the controller as a finite state machine, using visualSTATE.
The source lies at this link: