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Low power VLSI design

General information on the research area:
Low power VLSI design is important for further increase of complexity and performance in future VLSI chips and Systems-on-Chip(SoC). For mobile equipment the limited battery capacity is restricting power budgets and performance, while for high performance systems and chips, the heat dissipation problems are restricting circuit complexity, packing density and achievable clock rates. Substantial power reduction may be achieved by clever system design including low-power data path, memory and bus optimisation and management; by use of agressive and dynamic voltage scaling; by introducing new circuit topologies; and by migration to newer process technologies (with down-scaled geometries).

We have proposed a low-power SoC strategy introducing the GALS-LDVS socket interface, which enables Globally-Asynchronous, Locally-Synchronous  (GALS) design in combination with the use of Locally Dynamic Voltage Scaling (LDVS) for each local synchronous module. By means of the GALS-LDVS socket, module reuse and system design may be simplified, while use of state-of-the-art synchronous design methods and synthesis tools may be continued.

Future SoC designs may typically have large memories, which will contribute substantially to the overall power consumption, performance and chip area. In cooperation with IMEC, Belgium, a novel storage requirementestimation and optimization methodology has been proposed for use in the early system design phases. The designer is assisted during the search for system solutions with low storage requirements.

Future deep-submicron SoC designs require low-voltage circuit operation. The design of analog building blocks and data converters (A/D,D/A) is considered especially challenging to satisfy the required  S/N-ratios at low supply voltages. Also special floating-gate techniques is currently explored in cooperation with University of Oslo. Moreover, the design of low-voltage digital cells may include the introduction of multiple threshold voltages, and other means to limit the leakage power in large, deep-submicron SoC designs.

It is belived that complex future SoC may only be successful by introducing novel extensive Built-In-Self-Test (BIST) methodologies. Since the power consumption in the BIST execution phase may be excessive due to higher signal transition activity than in normal operation modes, new low-power BIST architectures and new BIST scheduling principles have to be explored.

The proposed GALS-LDVS socket interface (Proc. 14th IEEE ASIC/SoC Conference, Washington DC, Sept. 2001)

Dynamic voltage scaling in a burst-based digital radio (Proc. IST Mobile Summit 2001, Barcelona, Spain, Sept. 2001)

”Data and memory optimization techniques for embedded system"   (ACM Transactions on Design Automation of Electronic Systems, Vol. 6, No 2, April 2001, pp 149 – 206)

VLSI for digital signal processing

Ph.D. Course "DIE4937 Low-power VLSI for DSP Applications" (offered since 1998)

Low voltage, low power digital VLSI circuit design and methodology
(http://www.fysel.ntnu.no/Cas/lplv_digital.html (N/A yet))

Memory estimation methodology (in cooperation with IMEC, Belgium):
(http://www.fysel.ntnu.no/Cas/memory_estim.html (N/A yet))

Built-In-Self-Test (BIST) Methodology:
(http://www.fysel.ntnu.no/Cas/bist_methodology.html (N/A yet))

Low voltage analog circuit design
(http://www.fysel.ntnu.no/Cas/lplv_analog.html (N/A yet))

Direct link to ongoing research projects involving low-power digital VLSI design:
WIRAC - Wideband Radio Access
ASPIC - Applied Signal Prosessing in Communications

The Ciruits and Systems Group at Dept. of Physical Electronics, NTNU, has (by Sept 2001) been appointed as Marie Curie Training site for "System-on-Chip Design for Smart Applications".